1. Field of the Invention
The present invention relates to a method of manufacturing a microelectronic package, particularly a microelectronic package incorporating two or more microelectronic elements, e.g., semiconductor chips, especially in a face-down orientation relative to a dielectric element or package substrate.
2. Description of the Related Art
Semiconductor chips are thin flat bodies incorporating a semiconductor device region over which wiring layers are provided in dielectric layers overlying the semiconductor device region and on which contacts at a face of the semiconductor chip are typically provided above the wiring layers and the device region. As used in this disclosure with reference to a component such as a dielectric element or other component such as a semiconductor chip having dielectric material at a surface thereof, a statement that an electrically conductive element is “at” a surface of the component indicates that, when the component is not assembled with any other element, the electrically conductive element is available for contact with a theoretical point moving in a direction perpendicular to the surface of the component toward the surface of the component from outside the component. Thus, a terminal or other conductive element which is at a surface of a component may project from such surface; may be flush with such surface; or may be recessed relative to such surface in a hole or depression in the component.
Microelectronic elements such as semiconductor chips, and semiconductor chips which have one or more wiring layers (e.g., in a redistribution structure) on a face thereof coupled to the contacts of the chip, are commonly combined with dielectric and conductive structure to form microelectronic packages. Each microelectronic package includes electrically conductive structure interconnecting the microelectronic element(s) of the package with terminals provided at a surface of the package, the terminals being configured to electrically connect the package with another component such as a circuit panel, among others.
Microelectronic elements can include one or more memory storage arrays that permit data to be written to a storage array and read from a storage array through the contacts at the face of the microelectronic element. One such type of semiconductor chip having memory storage arrays is a dynamic random access memory (“DRAM”) chip. With reference to a microelectronic package 10 shown in FIG. 1, the contacts 35 of a DRAM chip 30 are commonly provided in a row of contacts, or sometimes two or more parallel rows of contacts disposed at or near a midpoint of a distance between opposite parallel edges 32a, 32b of the chip. In the multi-chip package 10 seen in FIG. 1, two microelectronic elements, viz. semiconductor chips 30, 31, can be affixed within the package 10 in a back to back configuration overlying a substrate 11. Each microelectronic element 30, 31 is shown having contacts 35, 35′, respectively, at faces 19 of the chips 30, 31, the contact-bearing faces 19 of the chips 30, 31 being oriented in oppositely facing directions which face away from the other chip. In the case of upper chip 31, a redistribution structure 37 may couple the contacts 35′ thereof with redistribution contacts 36 provided on the face 19 of chip 31 adjacent to the peripheral edges 32a, 32b thereof. Wire bonds 42 couple the redistribution contacts 36 to substrate contacts 41 at a surface of substrate 11. As further seen in FIG. 1, terminals 40 of the package 10 can be electrically coupled with the contacts 35 of the lower chip through leads 38 such as wire bonds and other electrically conductive structure on the substrate 11, e.g., bond pads 39 and traces (not shown).
In high volume manufacturing, processing to produce package 10 must be performed in a specific sequence. As depicted in FIG. 2, in block 102 this processing includes picking a first die (microelectronic element 30) from a first wafer and placing and attaching the microelectronic element 30 in a face-down orientation facing a surface 44 of substrate 11, such as with an adhesive. Thereafter, in block 104, a second die (microelectronic element 31) is picked from a second wafer and placed and attached in the face-up orientation atop microelectronic element 30 such as with an adhesive. The substrate then is inverted so that the face 19 of microelectronic element 30 faces up. In block 106, a first set of wire bonds 38 can be formed which electrically couple contacts 35 of the lower chip 30 with corresponding contacts 39 on the substrate 11. Subsequently, in block 108, the substrate is inverted again so that face 19 of microelectronic element 31 faces up and thereafter in block 110 another set of wire bonds is formed connecting the RDL contacts 36 of microelectronic 31 with other contacts 41 on substrate 11.
In high volume manufacturing, processing to produce package 10 must be performed in a specific sequence. As depicted in FIG. 2, in block 102 this processing includes picking a first die (microelectronic element 30) from a first wafer and placing and attaching the microelectronic element 30 in a face-down orientation facing a surface 44 of substrate 11, such as with an adhesive. Thereafter, in block 104, a second die (microelectronic element 31) is picked from a second wafer and placed and attached in the face-up orientation atop microelectronic element 30 such as with an adhesive. Thereafter, in block 106, a first set of wire bonds can be formed which electrically couple redistribution contacts 36 of the upper chip 31 with corresponding contacts 41 on the substrate 11. Subsequently, in block 108, the substrate then is inverted so that the face 19 of microelectronic element 30 faces up, and thereafter in block 110 another set of wire bonds 38 is formed connecting the contacts 35 of microelectronic 30 with other contacts 43 on substrate 11.
Referring now to FIG. 3, in a second type of multi-chip microelectronic memory package 210 according to the prior art, two microelectronic elements (e.g., dies or chips 230, 231) are vertically stacked above a surface 244 of package substrate 211 and each has a contact-bearing face 219 which faces upwardly away from the surface 244 of substrate 211. In this case, because the faces 219 of each of the chips 230, 231 faces up, i.e., away from the substrate 211, a spacer element 233 may be needed to provide and maintain a desirable standoff height H between the face 219 of the lower chip 230 and a rear face 221 of the upper chip 231 to accommodate wire bonds 242 which couple contacts of the lower chip 230 with corresponding contacts 241 of the substrate 211.
As further seen in FIG. 4, a common method of manufacturing the package 210 can include in block 202 placing and attaching a first die or first microelectronic element from a first wafer face up above surface 244 of the substrate, and thereafter in block 204 placing and attaching a spacer element 233 overlying the contact-bearing face 219 of the first microelectronic element 230. Then, in block 206 wire bonds 242 are formed which couple the contacts of the first microelectronic element 230 with substrate contacts 241. The wire bonds must be formed before the spacer element 233 is attached. Thereafter, block 208 provides placing and attaching a second die or second microelectronic element 231 taken from a second wafer face up on the substrate, after which block 212 provides forming wire bonds which electrically couple the second microelectronic element 231 with contacts 241 of the substrate.
In high volume manufacturing of multi-chip packages as shown in FIGS. 1 and 3, it is not possible for the microelectronic elements 30, 31, or for the microelectronic elements 230, 231, to be taken from the same wafer and combined together in the same microelectronic package. In high volume manufacturing, each manufacturing step of placing a die or spacer element as indicated in FIGS. 2, 4, ordinarily must be performed at a different station than a station at which wire bonds are formed. Therefore, a sequence which involves performing a step at one station of placing a die and then performing a step at another station of forming wire bonds, and then performing another step of placing a die will not be capable of forming packages in a way that ensures that two dies from the same wafer will be placed within the same package.
Moreover, referring again to FIG. 2, the steps required to form the package 10 shown in FIG. 1 do not result in two dies from the same wafer being placed in the same package 10 in high volume manufacturing because the dies have front faces 19 which are oriented in respective opposite directions. Tooling used to transfer dies from one wafer for assembly with package substrates must either be set up for transfer of the dies in a face-down orientation relative to the substrates, or transfer of the dies in a face-up orientation relative to the substrates, but cannot do both. Therefore, the dies 30, 31 assembled in package 10 must be obtained from two different wafers due to different orientations required for each die.
Moreover, since the upper die 31 has a different pattern of contacts 36 thereon than the contacts 35 of the lower die 30, the dies 30, 31 cannot be obtained from the same wafer in high volume manufacturing, as the contacts 36 are formed at wafer-level before the wafer has been diced into individual dies. Moreover, in a case in which the contacts 36 are redistribution contacts coupled to central contacts 35′, such redistribution contacts would also be formed at wafer-level and thus, dies 30, 31 would not be from the same wafer in that case either.
Size is a significant consideration in any physical arrangement of chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” and “tablet computers” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/O's.” These I/O's must be interconnected with the I/O's of other chips. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines. For example, structures which provide numerous short, interconnects between complex chips can increase the bandwidth of the search engine and reduce its power consumption.
In view of the foregoing, further improvements can be made to improve the manufacturing of multi-chip microelectronic packages, particularly those which include microelectronic elements having memory storage arrays.